2, for a DRAM device, the pattern of the gate electrode 22b in the peripheral circuit region 20b is at once parallel to the flat zone 21 and arranged in a direction orthogonal to the flat zone 21. Bold arrow 24 indicates a halo ion implantation direction in which the halo ions are not implanted into the sources/drains 23a.Ī detailed description thereof is as follows.Īs shown in region 20b with a low concentration of pattern in FIG. 2 indicates an ion implantation direction in which the sources/drains 23a and 23b are exposed to the halo ion implantation when the halo ions are implanted. Additionally, gate electrode 22b and impurity regions 23b are illustrated on the region 20b with a relatively low concentration of pattern.įurthermore, arrow 25 in FIG. ![]() Reference numeral 23a shown on both sides of the gate electrode 22a represents an impurity region 23a operating as a source/drain of a transistor. Gate electrodes 22a are concentrated on the region 20a with a high concentration of pattern. ![]() A region 20a with a high concentration of pattern(gate electrode) such as a cell array region of a DRAM device is illustrated on the left side of the dotted line, and a region 20b with a relatively low concentration of pattern as compared with the cell array such as a peripheral circuit region of a DRAM device is illustrated on the right side of the dotted line. Reference numeral 20 represents a wafer and reference numeral 21 is a flat zone. 2 illustrates an example of a layout of a conventional semiconductor device. In a conventional DRAM device fabrication process, when drawing a layout of a transistor, the layout is arranged in a vertical or horizontal direction from a flat zone of a wafer.įIG. The halo ion implantation process can be explained in detail as follows. The deep impurity layer is called a source/drain of a transistor, and the shallow impurity layer is usually called a Lightly Doped Drain(LDD) in a semiconductor fabrication process. Then, by using the sidewall spacer 105 as a mask, a second conductive type impurity ions are implanted into the semiconductor substrate 100 and heat-treated, thus forming a deep impurity layer 106 with a relatively deep junction depth as compared with the shallow impurity layer 103. 1 c, a sidewall spacer 105 formed of an insulating film is formed on the sidewalls of the gate electrode 102. Generally, in order to form the halo ion implantation layer within the gate electrode 102, impurity ions are implanted at approximately 25-30 degree angle(that is, &thgr =25˜30°) from a vertical direction of the semiconductor substrate. At this time, the incidence angle leaned at 25-30 degrees is called an angle of inclination, and indicated as &thgr in FIG. At this time, to implant halo ions into a lower side of the gate electrode 102, an ion implantation is carried out at approximately 25˜30 degree angle from a direction vertical to the surface of the semiconductor substrate 100. 1b, the impurity ions of the same conductive type as that of the semiconductor substrate 100, that is, the first conductive type(p-type) impurity ions are implanted near the sidewalls of the shallow impurity layer 103 below the gate electrode 102, thus forming a halo ion implantation layer 104. The second conductive type impurity ions are opposite to the first conductive type impurity ions. n-type) impurity ions are implanted into the semiconductor substrate and heat-treated, thus forming an impurity layer 103 with a relatively shallow junction depth as compared with sources/drains which will be explained in the following process step. Next, using the gate electrode 102 as a mask, a second conductive type(e.g. 1a, a gate oxide film 101 and a gate electrode 102 are formed on a first conductive type(e.g. ![]() 1a through 1c, a conventional halo ion implantation method will be explained as follows.Ī shown in FIG. As a result, the impurity concentration of the semiconductor substrate near the inside sidewalls of the sources/drains becomes higher than that of the semiconductor substrate in other part. The present invention relates to a fabrication method for a semiconductor device, in particular to a halo ion implantation method for a semiconductor device which enhances data maintenance characteristics by not allowing sources/drains of a cell transitor of a Dynamic Random Access Memory(hereinafter DRAM) to be exposed to the halo ion implantation.Ī halo ion implantation means implanting conductive impurity ions identical with a semiconductor substrate into the semiconductor substrate along the inside sidewalls of sources/drains of a transistor in order to prevent a short channel effect.
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